Integrated circuits are often formed on a semiconductor substrate, such as a silicon wafer or other semiconductive material. In general, various materials such as semiconductive, conductive, or electrically insulative materials, are used to form integrated circuits. By way of example, the various materials may be doped, ion implanted, deposited, etched, grown, etc., using various processes. A continuing goal in semiconductor processing is to reduce the size of individual electronic components, thus enabling smaller and denser integrated circuitry.
Fabrication of advanced 3-D semiconductor structures with complex surface topology and high packing density is populated with complex technical challenges. For example, many challenges exist for metal and dielectric etching, including directed reactive ion etching (DRIE) with high selectivity. One common characteristic of these processes is treatment of vertical surfaces with angled ion beams. Depending on the device structure, especially high aspect ratio structures, difficulty can be experienced in obtaining a uniform ion flux from top to bottom across the entire vertical sidewall. This problem occurs especially where the device aspect ratio causes shadowing of the ion beam, thus attenuating or blocking the ion flux to the lower portions of the vertical device features.
In some current art approaches, the above issues are mitigated by using multiple recipe steps along with decreasing ion beam angle. For example, ion beam angles may be modulated by tuning extraction voltage, source power and z-gap. Returning to the set-up process multiple times to create different ion beam angles is time consuming and reduces throughput in high volume manufacturing (HVM) processes.